1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention relates to techniques for improving the fabrication of conductive contacts to gate electrodes and diffusion regions in high performance devices.
2. Description of the Related Art
In fabricating semiconductor devices, semiconductor wafers are placed through a multitude of fabrication operations in order to produce a desired integrated circuit device. As integrated circuit devices continue to shrink, design engineers are continually required to push the limit on existing fabrication techniques. By way of example, when transistor devices are designed with smaller and smaller drain and source diffusion regions, the conductive contacts (i.e., defined through silicon dioxide) that are designed to make electrical links with selected diffusion regions sometimes experience misalignments. Because standard photolithography techniques are now being pushed to their physical limits, these misalignments are expected. Therefore, in order to avoid making an unwanted electrical contact with a gate electrode when a misalignment occurs, a self-aligned contact (SAC) fabrication process has now become common practice. For ease of description, a conventional SAC fabrication process is discussed with reference to FIGS. 1A-1E.
FIG. 1A shows a cross sectional view 100 of a semiconductor substrate 102 having several fabricated layers illustrating a exemplary self-aligned contact (SAC) in accordance with a conventional semiconductor fabrication technique. In this example, the semiconductor substrate 102 has two shallow trench isolation regions (STI) 104a and 104b, which are conventionally used to isolate the various semiconductor transistor devices fabricated throughout a semiconductor wafer. Also shown are two transistor devices having polysilicon gates 108a and 108b. The transistor device having polysilicon gate 108a is shown having diffusion regions 106a and 106b which are used to define the source and drain regions of the transistor device. The transistor device having polysilicon gate 108b is shown partially lying over the shallow trench isolation region 104b, which is better defined by a cross section A--A of FIG. 1B.
As shown in a top view of FIG. 1B, the polysilicon gate 108b has a contact region in which a contact 109b may be made to the polysilicon gate 108b (i.e., over a poly head). However, the contact 109a is a self-aligned contact (SAC) which enables the formation of a via hole down to the diffusion region 106b without exposing the polysilicon gate 108a. In this example, contact 109a is shown misaligned because the design rules of smaller devices typically causes such misalignments. In contrast, older generation devices had larger geometric sizes, and therefore, the via holes down to the diffusion regions usually did not accidentally misalign over the polysilicon gates and cause circuit malfunctions.
Referring back to FIG. 1A, the polysilicon gates 108a and 108b have an oxide layer 110 defined along the sidewalls and the top surfaces of the polysilicon gates 108. The oxide that remains along the sidewalls of the polysilicon gates 108a and 108b are commonly referred to as oxide spacers. Once the oxide material 110 has been defined, a silicon nitride layer 112 is formed over the semiconductor substrate including over the oxide material 110. Also shown is a dielectric layer 114 that is defined over the silicon nitride layer 112. In order to define the via holes through the dielectric layer 114, a photoresist mask 116 (having expected misalignments) is used to identify the locations where contact 109a and 109b will ultimately reside. After the photoresist mask 116 has been defined, a dielectric etch operation is performed which selectively removes the exposed dielectric material 114 and stops at the silicon nitride layer 112. At this point, a second etching operation is performed (using a different etch chemistry) to etch through the silicon nitride layer 112 as shown in FIG. 1C.
This silicon nitride etch will continue until the exposed silicon nitride layer 112 is removed from within the via holes that define the contact locations 109a and 109b. As shown, the silicon nitride layer will be removed until the oxide material 110 and diffusion region 106b is exposed within the via holes. At this point, a clear path will be made down through the via hole of contact 109a, which defines a path down to the diffusion region 106b (without exposing the polysilicon gate 108a). However, electrical contact is also desired down to the polysilicon gate 108b through the via hole that defines the contact 109b.
To accomplish this, a typical prior art approach has been to spin-coat a new photoresist layer 116' over the semiconductor substrate, which substantially fills the via holes that define paths to the contacts 109a and 109b. The photoresist layer 116' is then patterned using a conventional photolithography process which is configured to make the photoresist layer 116' lying over the contact 109b more soluble during a subsequent photoresist development operation (in some cases, photoresist may also become trapped within the via hole of contact 109b). When the photoresist material 116' mask is complete and ready for etching, the via hole of the contact 109a will remain filled with photoresist. Next, a dielectric etch is performed to remove the dielectric material 110 that remains over the polysilicon gate 108b, which will enable subsequent electrical contact to be made when a conductive via is formed in the via hole of contact 109b. Once the dielectric etch is complete and the oxide material 110 is removed from over the polysilicon gate 108b, the photoresist material 116' is stripped.
Unfortunately, because some via holes such as those of contact 109a are sometimes quite deep (i.e., have large aspect ratios), conventional photoresist stripping operations may inadequately remove all of the photoresist material from within the via holes. As shown in FIG. 1E, a residue of photoresist material 116' remains at the bottom corners (and sometimes over the entire bottom surface) of the via hole of the contact 109a. Hence, the tungsten plugs 118a and 118b defined in the via holes of the contacts 109a and 109b will necessarily suffer by exhibiting high contact resistances and reduced reliability. Furthermore, as demands for smaller integrated circuit devices continue to increase, the contact via holes will exhibit larger aspect ratios which will necessarily make it more likely that photoresist residues will be trapped within via holes. As a result, the conductive contacts throughout an integrated circuit design will exhibit higher resistances that will prevent the device from operating at higher speeds.
In attempts to combat the problem of trapped photoresist residue in via holes, fabrication engineers have been forming the contacts that are made down to the drains and sources, and the polysilicon gates during different fabrication cycles. For example, after the dielectric layer 114 is deposited over the semiconductor substrate 102, only via holes down to the source and drain diffusion regions are made. As mentioned above, the process of making an electrical contact down to the diffusion regions requires utilizing two separate etching operations in order to first etch through the dielectric layer 114 and then through the silicon nitride layer 112. Once those etching operations are complete, the tungsten plugs 118a are formed, and a CMP operation or a tungsten etch-back operation is used to remove the excess tungsten material after filling the contacts down to the diffusion regions.
Once the formation of all of the contacts down to the sources and drains is complete for a particular integrated circuit device, via holes are then defined down to the polysilicon gates 108b. To define this via hole, three separate etching operations are utilized in order to etch though the dielectric layer 114, the silicon nitride layer 112, and then the oxide material 110. Once the formation of these via holes is complete and a path is made down to the polysilicon gate 108b, tungsten plugs 118b are formed. After the tungsten deposition is complete, a CMP operation or tungsten etch-back is again performed in order to remove the excess tungsten material.
Although forming contacts to diffusion regions and gate electrodes during different process cycles may produce more reliable interconnect structures, the number of process operations performed to form all of the contacts is essentially doubled. Furthermore, when a semiconductor wafer is placed through more process operations, the previously formed layers are subjected to processing stresses and heat operations that may introduce reliability reducing side effects, and may therefore reduce yield.
In view of the foregoing, there is a need for methods that improve the fabrication efficiency of conductive contacts made to diffusion regions and transistor gate electrodes throughout a semiconductor integrated circuit device.